Modern semiconductor devices may comprise thousands or even millions of components (e.g., transistors, interconnects, pads, etc.) integrated into a single die. As such, semiconductor real estate is a premium asset not to be squandered by an integrated circuit (“IC”) designer. To maximize the useable real estate of a single die, components may be integrated onto the front side as well as the backside of the die. To interconnect a dual sided die, through-wafer vias are formed throughout the die coupling the topside of the die to the bottom side of the die.
Another technique used to maximize the number of components within a single device is to stack two or more semiconductor dice together in what is called a bonded wafer stack. Components within these bonded wafer stacks are then interconnected using through-wafer vias. Known techniques form these through-wafer vias with a deep reactive ion etching process, requiring expensive tools. Not only is deep reactive ion etching expensive, but it is a slow fabrication technique.
Redistribution features (e.g., transmission lines) are often formed on the surface of a die to couple a via to other component locations. Current processes struggle with the challenge of coating straight sidewalls with metal to form the redistribution features. Typically, thicker metal layers are deposited to overcome these coating issues, with the detrimental side effect of increased incidence of stress induced wafer breakage. Known processes use additional lithography and metal plating processing, separate from via formation, to form these redistribution features. Similarly, known techniques require that the metallization of the vias be patterned after via formation using an additional high-aspect-ratio lithography process.